This invention relates to a semiconductor memory device and more particularly to a nonvolatile semiconductor memory device having ferroelectric capacitors.
Recently, semiconductor memories are widely used in various portions such as the main storages of large-scale computers, personal computers, domestic products, portable telephones and the like. As the types of semiconductor memories, a volatile DRAM (Dynamic RAM) and SRAM (Static RAM), nonvolatile MROM (Mask ROM) and flash E2PROM are on the market. Particularly, even though DRAM has a defect in which information cannot be maintained when the power supply is cut off since it is a volatile memory, it is excellent in its low cost (the cell area is xc2xc times that of an SRAM) and high operation speed (in comparison with flash E2PROM) and DRAMs have a dominant share of the market. The flash E2PROM which is a rewritable nonvolatile memory can maintain information even if the power supply is cut off, but since it has a defect in which the number of rewriting operations (W/E number) is only approx. 10 to the sixth power, the write time is approx. some microseconds and an application of high voltage (12V to 22V) is required for data writing, flash E2PROMs do not dominate the market as much as DRAMs.
Since a nonvolatile memory (ferroelectric RAM) having ferroelectric capacitors has various advantages that it is nonvolatile, the number of rewriting operations is 10 to the twelfth power, the readout/write time is approximately equal to that of DRAM and the operation voltage is 3V to 5V, it may take the lion""s share of the memory market and various makers have developed ferroelectric RAMs since they were proposed in 1980.
FIG. 1 shows a memory cell with the construction of one transistor and one capacitor in the conventional ferroelectric memory and a cell array construction. The construction of the memory cell MC in the conventional ferroelectric memory is obtained by connecting the current path of a cell transistor CT in series with a cell capacitor (ferroelectric capacitor) FC. A cell array CA includes bit lines BL, /BL for reading out data, word lines WL0, WL1 for selecting the cell transistors CT, and plate lines PL0, PL1 for driving one-side electrodes of the ferroelectric capacitors FC. A row decoder (more precisely, row decoder and plate driver) RD for driving the word lines WL0, WL1 and plate lines PL0, PL1 is arranged on one end of the cell array CA.
FIG. 2 shows an example of the structure of the memory cell MC. The ferroelectric capacitors FC includes a bottom electrode BE (plate electrode PL), ferroelectric material film FE and top electrode TE and the top electrode TE is connected to a metal interconnection M1 via a contact TW. The metal interconnection M1 is connected to an active area AA used as the drain of the cell transistor CT via a contact AW. Another active area AA used as the source of the cell transistor CT is connected to a metal interconnection M1 via a contact AW and the metal interconnection M1 is connected to a bit line /BL formed of a metal interconnection M2 by a contact VIA.
With the cell array construction of FIG. 1 and the memory cell structure of FIG. 2, the following problem occurs. That is, since the word lines WL0, WL1 are formed by extending the gate electrodes of the cell transistors CT, it is difficult to form gate interconnection layers with low resistance, and as a result, the sheet resistance thereof becomes several ohms/xe2x96xa1 or more. Therefore, if an attempt is made to reduce the chip size by increasing the area of the memory cell array mat and lowering the ratio of the area of the row decoder RD, an amount of gate delay becomes excessively large. Likewise, since the plate lines PL0, PL1 are formed of a material such as Pt, Ir, IrO2, Ru, StRuO, the sheet resistance thereof becomes several ohms/xe2x96xa1 or more. Therefore, if an attempt is made to reduce the chip size by increasing the area of the memory cell array mat and lowering the ratio of the area of the row decoder RD, an amount of delay by the plate lines PL0, PL1 becomes excessively large.
In order to solve the above problem, a word line shunt system used in the DRAM or the like or a hierarchical word line system shown in FIG. 3 may be used.
FIG. 3 is a block diagram showing a cell array of a ferroelectric memory using the hierarchical word line system. The cell array CA is divided into a plurality of sub-cell arrays SCA and sub-row decoders (sub RD) SRD are respectively disposed for the sub-cell arrays SCA. A circuit for driving sub-word lines SWL0 to SWL3 used as the gates of the memory cell transistors in the sub-array SCA is arranged in the sub-row decoder SRD. On one-end side of the cell array CA, a main row decoder (main RD) MRD is disposed and main word lines MWL0, MWL1 are formed to extend from the main row decoder MRD over the cell array CA and connected to each of the sub-row decoders SRD. The sub-row decoders SRD derive the logical product of signals supplied via the main word lines MWL0, MWL1 and signals (word line driving signals) selectively supplied via word line driving signal lines MDV0 to WDV7 to generate driving signals SWL0 to SWL3. For example, when the signal of the main word line MWL0 is at the high level and the signal of the word line driving signal line MDV0 is set at the high level, the signal of the sub-word line SWL0 is set to the high level.
With the above construction, only a simple decode circuit and driver circuit are arranged in each of the sub-row decoders SRD and a decode circuit for selecting one of a plurality of main word lines MWLi (i=0, 1, . . . ) according to an external address can be commonly arranged in the main row decoder MRD. As a result, the number of row decoder circuits can be reduced in comparison with the cell array construction shown in FIG. 1, the area of the sub-row decoder SRD can be reduced and the chip size can be reduced while the operation speed is maintained. Likewise, the area of the sub-row decoder SRD in the plate line driving circuit can be reduced.
However, in the above system, as shown in the cross sectional view of the memory cell MC in FIG. 4, only a structure in which a metal interconnection M3 is newly formed above the metal interconnection M2 and the main word line MWL is formed to extend to various portions can be used, and as a result, an additional process step of forming the metal interconnection layer is necessary, which raises the production costs.
Thus, in the conventional ferroelectric memory, there occurs a problem that the chip area increases if the hierarchical word line system is not used and the process cost rises if the hierarchical word line system is used.
The inventor of the present application has proposed a new ferroelectric memory which is nonvolatile and simultaneously attains the three features of (1) small memory cells of 4F2 size, (2) plane transistors which can be easily formed and (3) highly flexible random access function in Jpn. Pat. Appln. KOKAI Publication No. 10-255483 (U.S. Pat. Nos. 5,903,492 and 6,094,370 which were filed based on the prior application used as part of the basic application and are now pending) which is a prior application of the present application.
FIGS. 5A and 5B show examples of the construction and operation of the ferroelectric memory relating to the prior application. In the prior application, each memory cell MC is constructed by connecting the current path of a cell transistor CT in parallel with a ferroelectric capacitor FC. One memory cell block MCB is constructed by serially connecting a plurality of parallel-connected memory cells MC, connecting one end thereof to a bit line /BL or BL via a block selection transistor BST and connecting the other end thereof to a plate line PL or /PL. The ON/OFF states of the cell transistors CT are controlled by selectively driving word lines WL0 to WL7 by outputs of a row decoder RD. The ON/OFF state of the block selection transistor BST is controlled by selectively driving a block selecting line BS0, BS1 by an output of the row decoder RD. The plate lines PL, /PL are driven by a plate driver (PL driver) PLD. A potential difference between the potentials of the bit lines /BL and BL is amplified by a sense amplifier SA. With this construction, a memory cell with minimum size of 4F2 can be realized by use of plane transistors.
With the above construction, when in standby, all of the word lines WL0 to WL7 are set at the high level to set the cell transistors CT in the ON state and the block selecting lines BS0, BS1 are set at the low level to turn OFF the block selection transistors BST. Thus, since both ends of each ferroelectric capacitor FC are short-circuited by the cell transistor CT which is set in the ON state, no potential difference occurs between both ends of the ferroelectric capacitor FC and storage polarization is stably maintained.
On the other hand, when active, only the memory cell transistor CT which is connected in parallel with the ferroelectric capacitor FC subjected to readout is turned OFF and the block selection transistor BST is turned ON. For example, if the ferroelectric capacitor C1 shown in FIG. 5A is selected as the memory cell capacitor FC, the word line WL6 is set to the low level as shown in FIG. 5B. After this, the potential difference between the plate line /PL and the bit line /BL is applied only across the ferroelectric capacitor FC which is connected in parallel with the memory cell transistor CT set in the OFF state by setting the plate line /PL to the high level and setting the block selecting line BS0 to the high level and polarization information of the ferroelectric capacitor C1 is read out to the bit line /BL. Thus, even if the memory cells MC are serially connected, cell information of a desired one of the ferroelectric capacitors FC can be read out by selecting a desired one of the word lines and complete random access can be attained.
However, the same problem as that occurring in the construction shown in FIGS. 1 to 4 occurs in the ferroelectric memories with various constructions disclosed in the prior application. The pattern layout of the memory cells in the circuit construction of FIG. 5A is shown in FIG. 6 and the cross section of FIG. 6 is shown in FIG. 7. In FIG. 7, only a high-resistance material can be used as a material of the gate electrode GC (gate interconnection) of the memory cell transistor, a metal interconnection M1 is used as the cell interconnection of the memory cell and a metal interconnection M2 is used as the bit lines BL, /BL. Therefore, if an attempt is made to apply the hierarchical word line system or hierarchical plate line system as shown in FIG. 3, then it becomes necessary to form a new metal interconnection M3 used as the main-block selecting line or main word lines MWL0, MWL1 as shown in FIG. 7.
If an attempt is made to apply the hierarchical word line system or hierarchical plate line system to reduce the chip area in the conventional semiconductor memory device, there occurs a problem that a new interconnection layer becomes necessary and the process cost rises.
The above problem can not be solved by use of the ferroelectric memory disclosed in the prior application for realizing high integration while maintaining simplification of the manufacturing method and the random access function, and if an attempt is made to apply the hierarchical word line system or hierarchical plate line system to reduce the chip area, a new interconnection layer becomes necessary and the process cost rises.
According to an aspect of the present invention, there is provided a semiconductor memory device comprising a memory cell array which includes a plurality of sub-arrays, a plurality of sub-row decoders provided between the plurality of respective sub-arrays, for driving a plurality of sub-word lines, a main row decoder disposed on one-end side of the plurality of sub-arrays in a sub-word line direction, and a plurality of main-block selecting lines for respectively supplying outputs of the main row decoder to the sub-row decoders; wherein the plurality of sub-arrays each include the plurality of sub-word lines, a plurality of bit lines, a plurality of plate lines and a plurality of memory cell blocks, the plurality of the sub-arrays are arranged in the sub-word line direction, the memory cell blocks each include a plurality of series-connected memory cells and at least one selection transistor serially connected to at least one end of the series-connected portion, one end of each of the memory cell blocks is coupled to a corresponding one of the bit lines, the other end thereof is connected to a corresponding one of the plate lines, the gate terminal of each cell transistor is connected to a corresponding one of the sub-word lines, at least part of the main-block selecting lines is formed over the source, drain and gate electrode of the selection transistor, and the memory cell includes the cell transistor and a ferroelectric capacitor connected between the source and drain terminals of the cell transistor.